The present invention relates to a method for the measurement of the electrical characteristics of an object and a measurement apparatus utilizing the method.
In general, a known probe apparatus is an apparatus which uses a probe wire on a probe card to contact a bonding pad or the like provided to an object to be measured, and measures the electrical characteristics of semiconductor devices such as a semiconductor wafers.
FIG. 12 shows such a conventional type of probe apparatus, which has a structure including a holding means 4 which is freely movable in the X, Y and Z directions and has a wafer 2 loaded thereon, a probe apparatus 10 which has a probe card having a probe 6 in contact with a bonding pad of the wafer 2, and which is arranged above a holding means 4, and a test pad 14 which is hinged so as to be able to rise above the probe card 8 and be positioned to the side and above the probe apparatus 10. Test pad 14 is connected by wires 17 to a tester (not shown). In addition, instead of the hinge 12, a manipulator arranged to one side of the probe apparatus 10 can be used to support the test head 14 so that it can be raised and lowered (as for example, disclosed in Japanese Patent Publication (KOKOKU) No. 43854-1986, Japanese Utility Model Publication (KOKOKU) No. 4031-1991).
Testing the electrical characteristics of a wafer 2 by the conventional probe apparatus having the structure described above, is performed by first moving the test head 14 to the side above the probe card 8 so that the contact 16 mounted to the test head 14 comes into contact with the entrance/exit pin 18 of the probe card 8. Then, the probe 6 of the probe card 8 is brought into contact with the bonding pad 2a of the wafer 2 which has had its position adjusted by an alignment apparatus (not shown), and the tester (not shown) and which is connected to the test pad 16, measures the electrical characteristics of the wafer 2.
In a processing apparatus such as a supercomputer or the like, for which high speed is particularly important, it is necessary to shorten the internal wiring as much as possible to increase the processing speed. Instead of using a chip which resides within a package or the like, a semiconductor wafer is directly connected to an unpackaged cut chip using a connection method which not only increases the processing speed but also improves the mounting density. In this situation, an apparatus such as that shown in FIG. 12 is used to check the functions of each mounted chip by testing at the wafer level prior to cutting. However, it is known that heat, vibration and other damage sustained when there is cutting causes a decrease of about 0.1% in the yield. Sometimes an unpackaged chip which has proven reliable at the wafer level by testing prior to cutting, but after such a chip is mounted to a substrate is later judged to be faulty. There is the problem that the entire substrate has to be discarded since many unpackaged chips have already been mounted.
In addition, when the probe apparatus shown in FIG. 12 is used for testing at the wafer level, the operation is extremely complex since positioning of the cumbersome test head is different for testing a wafer, testing of characteristics of a chip, and testing of a packaged device.
Furthermore, when characteristics testing is performed at low temperatures (of -10.degree. C. to -55.degree. C. ) at the wafer level, a plural number of Peltier elements are used to cool the entire wafer. However, when all of the chips on a single wafer are being measured, other chips which have no role in the measurement, have to be cooled, thus there is a problem of poor efficiency, multiple failures of the Peltier elements, and low reliability.